1. Field of the Invention
The present invention relates to a frequency synchronous circuit, and more particularly, to a frequency synchronous circuit used for a digital synchronous network in a communication system.
2. Description of the Related Art
Recently, in accordance with the requirements for realizing a digital synchronous network in a communication system, a very stable clock signal (reference signal) must be transmitted. Therefore, it is required to provide a frequency synchronous circuit which can pick up and output an original clock signal by removing noise (noise components) caused in a transmission line by various factors.
In a prior art frequency synchronous circuit, a very stable PLL (Phase Locked Loop) circuit having a VCXO (Voltage-Controlled Crystal (X-tal) Oscillator) is used. Nevertheless, in this prior art frequency synchronous circuit, the PLL operation may fluctuate in accordance with various factors, for example, a jitter and wander (which is jitter with a frequency of less than 10 Hz), especially the wander.
Therefore, in the prior art frequency synchronous circuit (PLL circuit), the cut-off frequency of the PLL circuit is reduced in order to decrease the influences of jitter and wander. However, for example, when the cut-off frequency of the PLL circuit is reduced, a pull-in range becomes narrow, and further, the capacitor elements required for a circuit (lag filter or lag/lead filter) having a low cut-off frequency must be large.
For example, in a path protection switch ring system of SONET (Synchronous Optical Network) or SDH (Synchronous Digital Hierarchy), a working line and protection line are provided, and when trouble such an accident, device trouble, or construction work causes one line (working line), the other line (protection line) is automatically selected and used. However, in this path protection switch ring system, when changing from the working line to the protection line, the phase of the clock signal (reference signal) fluctuates, since the frequencies of clock signals of the working and protection lines are the same but the phases of the clock signals of the working and protection lines are generally different.
Further, in the prior art PLL circuit, when the reference signal is not transmitted due to, for example, trouble on a communication line, the PLL circuit is operated by the VCXO in a free-runnig mode, and the so-called hold-over function is not provided for the PLL circuit.
As explained above, in the prior art PLL circuit (frequency synchronous circuit), it is difficult for the lag filter or lag/lead filter to reduce the cut-off frequency so as not to change the output signal by the wander frequency without unnecessarily expanding the pull-in range thereof. Further, in the prior art frequency synchronous circuit, when changing the working line to the protection line, and the like, the clock signals therebetween must be changed. In addition, the hold-over function cannot be provided for the prior art frequency synchronous circuit.